The present disclosure relates generally to flip-flop designs, and more particularly to designs and methods that not only improve noise immunity but also reduce design space and power dissipation, thereby improving performance.
A flip-flop is an electronic circuit that stores a selected logical state in response to a clock pulse and one or more data input signals. Flip-flops are used in computational circuits. In these circuits, the flip-flops operate in selected sequences during recurring clock intervals to capture and hold certain data for a period of time sufficient for the other circuits within the system to further process that data. At each clock signal, data is stored in a set of flip-flops whose outputs are available to be applied as inputs to other combinatorial or sequential circuitry during successive clock signals. In this manner, sequential logic circuits are operated to capture, store and transfer data signals during successive clock signals.
Most flip-flops are designed to store data when a leading edge of a clock pulse is received, while some flip-flops store data on receipt of the trailing edge of a clock pulse. These flip-flops that store data at one of the aforesaid edges are known as single-edge-triggered flip-flops. Flip-flops that store data on both the leading edge and the trailing edge of a clock pulse are referred to as dual-edge-triggered flip-flops.
Electrical noise in either the data signal line or the clock line may cause the data signal to appear to change state at times other than at the rising or falling of the click signal, thereby causing bad data to be transferred and latched. One technique used to reduce the time of vulnerability is to generate a short duration pulse signal only as the clock signal rises or falls. However, the precision and repeatability required are too demanding. Another technique involves a master/slave mechanism. The second latch signal may be provided independently, but most typically, the original clock signal is inverted to provide a second rising latch signal as the original clock signal is falling. The first latch signal triggers a first pass gate, or the master, to transfer data to a first latch circuit for temporary storage. The second latch signal triggers a second pass gate, or the slave, to transfer data from the first latch circuit to a second latch circuit. This requires the construction of two latch circuits and their controls.
Many traditional designs of these circuits and their corresponding controls require more design space and more supply current. These designs are thus a liability in space- and power-conscious applications such as handheld devices. Therefore, desirable in the art of flip-flop designs are additional simpler designs that provide greater noise immunity with reduced design space.
Desirable in the art of semiconductor designs are additional switch designs that is faster, smaller, and consumes less electrical energy.